Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.
Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.
You will own the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet — the interconnect that lets our inference accelerators scale beyond a single package. This is a hands-on, transistor-level design role on a small team, where you will personally carry blocks from specification through silicon characterization rather than handing specs off to someone else. The work spans porting proven datapath blocks to new process nodes and ground-up design of new blocks for our next-generation link, working closely with layout, package/signal-integrity, backend, and firmware engineers to bring your designs to working silicon.
Own transistor-level design of the SerDes transmit path: output drivers (SST and/or CML), pre-driver and serializer stages, and transmit-side FFE.
Own transistor-level design of the receive front-end: termination and ESD-aware input network, CTLE, VGA, samplers, and where applicable ADC-based front-ends.
Design and verify the equalization path — DFE and FFE architecture, tap resolution, and adaptation behavior — and own the trade study behind the architecture you choose.
Derive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets, and defend those specifications in design review.
Build the verification environment for your blocks — testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation — and provide behavioral and Verilog-A models for full-chip verification, supporting backend engineers through integration.
Perform link and channel modeling in MATLAB, Python, or equivalent — S-parameter channel and package models, statistical eye and BER analysis, and equalization trade studies.
Drive layout of your blocks in deep sub-micron nodes, working with layout engineers on floorplan, matching, shielding, current density, and parasitic control, and co-designing with package/signal-integrity engineers on bump maps, escape routing, and channel budgets.
Contribute to testboard design, then take your blocks through silicon bring-up and bench characterization, correlating measured performance against simulation.
BS/MS/PhD in Electrical Engineering, with 8+ years of hands-on analog and mixed-signal circuit design experience.
Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link.
Deep knowledge of high-speed driver design, receive front-end design, and equalization, with practical familiarity with the adjacent clocking and CDR blocks your datapath interfaces with.
Practical command of jitter and noise analysis — decomposition, budgeting, and the simulation methodology to quantify each contributor.
Circuit design experience in advanced FinFET or GAA process nodes, with hands-on use of industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation) and link/channel modeling (e.g., MATLAB, Python, S-parameter models).
Silicon bring-up and bench debug experience with high-speed lab equipment such as scopes and BERTs, with the judgment to distinguish a design problem from a measurement problem.
Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including the specific constraints of short-reach, low-energy-per-bit links.
PAM4 signaling and DSP-based receiver architectures, including ADC-based front-ends.
Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7.
Experience porting a datapath block across process nodes, with a realistic sense of what that effort actually costs.
IBIS-AMI model generation, or SerDes ATE and production test development.
Participation in or contribution to standards bodies.
Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication, and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.